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Urgent! Contract Hardware Engineer Mid. Job Opening In San Jose – Now Hiring eTeam

Contract Hardware Engineer Mid.



Job description


ET_TN
Job Title: Contract Hardware Engineer Mid.

Location: San Jose, CA

Duration: months




Duties:



CW will work onsite from day San Jose ,CA

What candidate will Be Doing:

Technical:

Being a member of design team who oversees fullchip STA/ SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.

Option to also do block level RTL design or block or top-level IP integration.

Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.

Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.

Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.

Creating fullchip clocking diagrams and related documentation.

What we are looking for:



Minimum Qualifications

Bachelor’s Degree in Electrical or Computer Engineering with + years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with + years of ASIC or related experience

Experience with block/full chip SDC development in functional and test modes.

Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus

Understanding of related digital design concepts (eg.

clocking and async boundaries)

Experience with synthesis tools (eg.

Client DC/DCG/FC), Verilog/System Verilog programming

Preferred Qualifications

Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Client) and CCD (Conformal Constraint Designer from Cadence)

Experience with Spyglass CDC and glitch analysis

Experience using Formal Verification: Client Formality and Cadence LEC.

Experience with scripting languages such as Python, Perl, or TCL



Thanks


Required Skill Profession

Engineers



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