Hardware Engineering - Silicon Physical Design Engineer III

Role: Hardware Engineering - Silicon Physical Design Engineer III
Location: Remote

Duration: months(Possible for Extension)



Responsibility:

Strong understanding in the RTLGDSII flow and design tapeouts in nm/nm or below process technologies

• Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.



• Experience working with most EDA tools like DC/Genus, ICC/Innovus, Primetime, PTPX, Primepower Duties

• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.



• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution

• Power analysis based on netlist



Must Have Skills:

Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs

Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions and experience in chip power analysis

Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques and experience with Python, TCL, Perl programming



Nice to Have:

MSEE/CS or equivalent experience



Education:

Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science • Master's Degree preferred but not required



Interview:
Round: Technical with coder pad