Principal FPGA Verification Engineer $15K Sign On Bonus

Job description

**Job Description**

Minimum $15,000 Sign On Bonus being offered for external hires.

**US CITIZENSHIP REQUIRED**
#LI-LB3
The Engineering, Science and Analysis (ESA) Strategic Capabilities Unit comprises the technical talent and organizational leadership that enables the successful delivery of high-impact discriminating technologies for our customers missions.

Our collaborative, cross-functional teams are committed to innovation, integrity, continual learning and strong execution.

**What You ll Do:**

+ Apply innovative design techniques to create defense-oriented, cutting-edge electronic systems.
+ Work in a fast-paced team environment on a variety of R&D, proof of concept, and production programs.
+ Verify FPGA designs (including SOC architectures utilizing soft-core processors, digital filters, image processing algorithms, and communication interfaces/protocols), design and implement test benches for both unit level and system level environments, and create reusable verification environments that can be used across multiple projects.
+ Work in a System Verilog/UVM environment developing tests, testbenches, UVM components, and regressions/testlists.
+ Be responsible for generating and executing the FPGA Verification Test Plan and FPGA Verification Matrix.
+ Work collaboratively and in tandem with system architects, FPGA design engineers, and embedded software engineers.
+ Maintain a regular and predictable work schedule.
+ Establish and maintain effective working relationships within the department, the Strategic Business Units, Strategic Capabilities Units and the Company.

Interact appropriately with others in order to maintain a positive and productive work environment.
+ Perform other duties as necessary.

**On-Site Work Environment:** This position requires regular in-person engagement by working **on-site five days** each normally scheduled week in the primary work location.

Travel and local commute between company campuses and other possible non-company locations may be required.

**Working Conditions:**

+ Work is performed in an office, laboratory, production floor, or cleanroom, outdoors or remote research environment.
+ May occasionally work in production work centers where use of protective equipment and gear is required.
+ May access other facilities in various weather conditions.

**Required Education, Experience, & Skills**

+ BS degree or higher in Engineering or a related technical field is required plus 6 or more years related experience.
+ Each higher-level degree, i.e., Master s Degree or Ph.D., may substitute for two years of experience.

Related technical experience may be considered in lieu of education.

Degree must be from a university, college, or school which is accredited by an agency recognized by the US Secretary of Education, US Department of Education.
+ Solid FPGA/ASIC Verification development methodology.
+ Experience with System Verilog and UVM, and familiarity with electronic circuit design and electronic systems.
+ A solid understanding of object-oriented concepts and experience designing class-based constrained random test benches.
+ Experience with coverage writing (including coverpoints, crosses), coverage collection and improving coverage of the design under test.
+ Good communication skills, as well as excellent presentation skills.

A security clearance or access with Polygraph is not required to be eligible for this position.

However, the applicant must be willing and eligible for submission, depending on program requirements, after an offer is accepted and must be able to maintain the applicable clearance/access.

**Preferred Education, Experience, & Skills**

+ Experience with Modelsim/Questa simulator.
+ Experience in C object-oriented programming.
+ Knowledge and experience with Windows, Linux and scripting languages (e.g. Ruby, Python, TCL).
+ Experience in documentation and verification of high-speed digital electronics, FPGAs, and embedded processor systems.
+ Ability to develop specifications, cost, schedule, and resource requirements for FPGA or ASIC verification plans.
+ Familiarity with Signal Processing algorithms and DSP techniques.
+ Experience with cybersecurity topics/techniques.
+ Space or military experience.

**Pay Information**
Full-Time Salary Range: $115779 - $196825

Please note: This range is based on our market pay structures.

However, individual salaries are determined by a variety of factors including, but not limited to: business considerations, local market conditions, and internal equity, as well as candidate qualifications, such as skills, education, and experience.

Employee Benefits: At BAE Systems, we support our employees in all aspects of their life, including their health and financial well-being.

Regular employees scheduled to work 20 hours per week are offered: health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance.

We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance.

Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave.

Employees may participate in the company recognition program to receive monetary or non-monetary recognition awards.

Other incentives may be available based on position level and/or job specifics.

**Principal FPGA Verification Engineer - $15K Sign On Bonus**

**114981BR**

EEO Career Site Equal Opportunity Employer.

Minorities .

females .

veterans .

individuals with disabilities .

sexual orientation .

gender identity .

gender expression

Required Skill Profession

Other General