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Senior Design Verification Engineer Job Opening In Mountain View – Now Hiring Microsoft

Senior Design Verification Engineer

Job description

Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.

SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.

Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionateengineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance.

To achieve this goal, theArtificial Intelligence System on Chip (AISoC) Silicon teamis instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery,scaleand sustainability related to Microsoft cloud hardware.

We are looking for engineers with a dedicated passion for customer focused solutions,insightand industry knowledge to envision and implement future technical solutions that will manage andoptimizethe Cloud infrastructure.

We are looking for aSenior Design Verification Engineerto join the team.

Qualifications

Required/Minimum Qualifications:

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experienceOR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experienceOR Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experienceOR equivalent experience.

5+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals

3+ years of debugging RTL (Verilog) designs as well as simulation and/or emulation environments

3+ years experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C/C++ and Universal Verification Methodology (UVM)

3+ years experience with scripting language such as Python or Perl or shell scripts.

Other requirements:

Ability to meet Microsoft, customer and/or government security screening requirements arerequired for this role.

These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.

As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US.

residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.

To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport.

Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Additional or Preferred Qualifications

10+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental

In depth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments

Verification experience for an IP or SS or SOC related to CPUs, VPUs, GPUs, Tensor unit, or similar

Knowledge of System Verilog class, constraints, coverage and assertions.

Experience in scripting languages such as Python or Perl

Hands-on experience in Formal property verification, formal verification of computational data path designs

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year.

There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation.

Find additional benefits and pay information here:

Microsoft will accept applications and processes offers for these roles on an ongoing basis.

#SCHIE

Responsibilities

Perform pre-silicon verification for complex IP, including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.

Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP/SS/SOC level verification.

Define verification strategy, requirements, test environments for IP/SS/SOC level verification.

Create test-plans and write tests to provide complete features coverage.

Develop and implement technical solutions to complex quality and design challenges.

Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage.

Triage and debug testbench, simulation, and emulation fails.

Develop Makefiles and scripts for verification infrastructure.

Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.

Collaborate with teams across sites and geographies.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Industry leading healthcareEducational resourcesDiscounts on products and servicesSavings and investmentsMaternity and paternity leaveGenerous time awayGiving programsOpportunities to network and connect

Required Skill Profession

Engineers

Job Details

Company: Microsoft
Location: Mountain View, California, United States
Job Type: Full-Time
Salary: Undisclosed
Posted: 2025-10-08
Status: (Active)
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Industry: Engineers

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