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Urgent! Senior Technical Staff Engineer - Architect (Memory Interconnect) Job Opening In San Jose – Now Hiring Microchip Technology

Senior Technical Staff Engineer Architect (Memory Interconnect)



Job description

Are you looking for a unique opportunity to be a part of something great?

Want to join a 20,000-member team that works on the technology that powers the world around us?

Looking for an atmosphere of trust, empowerment, respect, diversity, and communication?

How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization?

We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world.

They stay because our culture supports their growth and stability.

They are challenged and driven by an incredible array of products and solutions with unlimited career potential.

Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually.

We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over without a great team dedicated to empowering innovation.

People like you.

Visit our page to see what exciting opportunities and company await!

Job Description:

Microchip Technology FPGA Business group is seeking a highly skilled and experienced Memory Interconnect System Architect to join our dynamic team.

The successful candidate will be responsible for leading cross-functional teams to deliver high-performance IP integrations into our FPGA products, that meet market & customer requirements across a broad range of use cases & application spaces.

This position is in the Silicon Architecture team of Microchip’s FPGA Division.

Microchip is a major supplier of low-power and highly-reliable field-programmable gate arrays (FPGAs).

Our FPGAs are used in a wide variety of applications, including embedded vision; digital signal processing; machine learning; industrial and medical equipment; and satellites.

Microchip is also a pioneer in embedding RISC-V processors in FPGAs.

The successful applicant will work as part a core team to develop future FPGA device products and will collaborate with other engineering disciplines to model, develop, verify, and integrate ​Interconnect components such as IO, hard Memory IP blocks, hard & soft IP solutions, that interoperate with overall configuration and security features to deliver performant FPGA products.

Key Responsibilities:

  • Lead cross-functional teams to deliver high-performance IP integrations into Microchip FPGA products
  • Work on architecture & implementation for Analog, ASIC & FPGA design development, integration, and deployment for high performance parallel interconnect, such as low voltage / high speed single ended and differential standards supporting protocols such as LP/DDR, LVDS, MIPI data & clocking.
  • Understand customer use cases and the role of IP in overall system architecture
  • Work cross-functionally with other architects, designers, and back-end implementation teams
  • Lead and manage other engineers in the team
  • Requirements/Qualifications:

  • MSc or higher in EE, CS, CE or other applicable disciplines
  • 12+ years of industrial experience
  • Proven experience in ASIC & FPGA IP development, integration, and deployment, including all stages of development from Synthesis, constraint management, place & route, floorplanning, timing closure, CDC/RDC
  • Knowledge and experience with system-level performance modeling in TLM/SystemC/Other will be an advantage
  • Experience in technical leadership and people management will be an advantage
  • Proven ability to work cross-functionally with other architects, designers, and back-end implementation teams
  • Knowledge and experience with Synopsys & Cadence ASIC flows
  • Scripting for EDA in Perl, Python, Tcl will be an advantage
  • Experience in technical leadership and people management will be an advantage
  • Travel Time:

    0% - 25%

    Physical Attributes:

    Feeling, Handling, Hearing, Seeing, Talking, Works Alone, Works Around Others

    Physical Requirements:

    10% standing, 10% walking, 80% sitting; 100% In-doors; Usual business hours

    Pay Range:

    We offer a total compensation package that ranks among the best in the industry.

    It consists of competitive base pay, restricted stock units, and quarterly bonus payments.

    In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.

    Find more information about all our benefits at the link below:The annual base salary range for this position, which could be performed in California, is $88,000 - $232,000.*

    *Range is dependent on numerous factors including job location, skills and experience.

    Microchip Technology Inc is an equal opportunity/affirmative action employer.

    All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

    For more information on applicable equal employment regulations, please refer to the .

    To all recruitment agencies:


    Required Skill Profession

    Engineers



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