Urgent! Senior Timing Methodology Engineer Job Opening In Santa Clara – Now Hiring NVIDIA
NVIDIA has continuously reinvented itself over two decades.
Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing.
More recently, GPU deep learning ignited modern AI — the next era of computing.
NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world.
This is our life’s work, to amplify human inventiveness and intelligence.
We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, informative analysis, and automation.
This work will influence the entire next generation computing landscape through critical contributions across NVIDIA's many product lines ranging from consumer graphics to self-driving cars and the growing domain of artificial intelligence! We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 5 nm and beyond, this is an ideal role.
What You'll Be Doing:
+ Improve and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and automation.
+ Develop custom flows for validating QoR of ETM models, both of std cells and custom IPs.
+ Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging, self-heating, thermal impact, IR drop etc.
+ Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.
+ Develop tools, and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.
+ Work on various aspects of STA, constraints, timing and power optimization.
What We Need To See:
+ MS (or equivalent experience) in Electrical or Computer Engineering with 3 years’ experience in ASIC Design and Timing.
+ Good understanding of modeling circuits for sign-off
+ Good knowledge of extraction, device physics, STA methodology and EDA tools limitations.
Good understanding of mathematics/physics fundamentals of electrical design.
+ Clear understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS), CDC, signal/power integrity, etc.
+ Understanding of 3DIC, stacking, packing, self-heating and its impact on timing/STA closure.
+ Background with crosstalk, electro-migration, noise, OCV, timing margins.
Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.
+ Understanding of standard cells/memory/IO IP modeling and its usage in the ASIC flow.
Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond.
+ Expertise in coding- TCL, Python.
C++ is a plus.
Familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc.
+ Strong communications skill and good standout colleague
With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers.
We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth.
Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology?
If so, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
You will also be eligible for equity and benefits (https://www.nvidia.com/en-us/benefits/) .
Applications for this job will be accepted at least until July 29, 2025.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer.
As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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Unlock Your Senior Timing Potential: Insight & Career Growth Guide
Real-time Senior Timing Jobs Trends in Santa Clara, United States (Graphical Representation)
Explore profound insights with Expertini's real-time, in-depth analysis, showcased through the graph below. This graph displays the job market trends for Senior Timing in Santa Clara, United States using a bar chart to represent the number of jobs available and a trend line to illustrate the trend over time. Specifically, the graph shows 184648 jobs in United States and 2184 jobs in Santa Clara. This comprehensive analysis highlights market share and opportunities for professionals in Senior Timing roles. These dynamic trends provide a better understanding of the job market landscape in these regions.
Great news! NVIDIA is currently hiring and seeking a Senior Timing Methodology Engineer to join their team. Feel free to download the job details.
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