Technical Staff Engineer - Layout (I/O Design-FPGA)

Are you looking for a unique opportunity to be a part of something great?

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People come to work at Microchip because we help design the technology that runs the world.

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They are challenged and driven by an incredible array of products and solutions with unlimited career potential.

Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually.

We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the and it’s won us countless awards for diversity and workplace excellence.

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Job Description:

Microchip Technology Inc.

is a leading provider of embedded control applications.

Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM).

We also license Flash-IP solutions that are incorporated in a broad range of products.

Microchip Technology Inc.

has a Technical Staff Engineer - Layout (I/O Design-FPGA) opening based in San Jose, CA.

The successful candidate will be responsible for layout design, integration, and verification of complex analog circuitry (clocking, Rx, Tx) integrated into the IO’s of the FPGA.

Responsibilities:

Layout complex analog circuits for GPIO, HSIO, high-speed DDR and other IO applications in advanced FinFET nodes.

Work with the I/O design lead, PnR team and other layout engineers in floor planning of IO banks including the distribution of critical signals and clocks, placement of different IO sub-blocks, and design of the IO power distribution network.

Collaborate closely with the design leads to understand the design requirements and implementing them in layout to meet performance specs.

Mentor and guide junior layout engineers in industry standard layout techniques of critical design blocks like Tx, Rx, PLL and other analog circuits.

Run DRC, LVS and EMIR and other checks.

The ability to customize DRC and LVS decks and knowledge of skill scripting is critical.

Layout guidance and mentorship of junior engineers.

Requirements/Qualifications:

Bachelors or Masters in electrical engineering, Physics, Computer Engineering or Computer Science preferred.

12+ years of proven silicon mask design experience in design of high-speed IOs in multiple technology nodes.

Experience in top level layout integration of SoC's or complex analog blocks like IOs that have significant analog and ASIC IPs.

Familiarity with FinFet technology.

Knowledgeable about industry standard tools like Virtuoso, skill scripting, Caliber, etc.

Experience in high-speed layout design techniques (DDRx, PCI-e, USB, MIPI).

Experience with skill scripting and customizing DRC/LVS decks.

Demonstrated competency in scripting using skill, Python and Perl.

Good analytical, oral and written communication skills

Able to write clean, readable presentations.

Self-motivated, proactive team player.

Ability to work to schedule requirements.

Travel Time:

0% - 25%

Physical Attributes:

Feeling, Hearing, Other, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

15% walking, 15% standing, 70% sitting, 100% in doors; Usual business hours

Pay Range:

We offer a total compensation package that ranks among the best in the industry.

It consists of competitive base pay, restricted stock units, and quarterly bonus payments.

In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.

Find more information about all our benefits at the link below:The annual base salary range for this position, which could be performed in California, is $88,000 - $232,000.*

*Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc is an equal opportunity/affirmative action employer.

All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the .

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